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DAC
2005
ACM
13 years 9 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
ICWS
2004
IEEE
13 years 8 months ago
Logic-based Web Services Composition: From Service Description to Process Model
This paper introduces a method for automatic composition of Semantic Web services using Linear Logic (LL) theorem proving. The method uses Semantic Web service language (DAML-S) f...
Jinghai Rao, Peep Küngas, Mihhail Matskin
IS
2006
13 years 7 months ago
Composition of Semantic Web services using Linear Logic theorem proving
This paper introduces a method for automatic composition of Semantic Web services using Linear Logic (LL) theorem proving. The method uses a Semantic Web service language (DAML-S)...
Jinghai Rao, Peep Küngas, Mihhail Matskin
IWQOS
2004
Springer
14 years 22 days ago
Provisioning servers in the application tier for e-commerce systems
Abstract— Server providers that support e-commerce applications as a service to multiple e–commerce websites traditionally use a tiered server architecture. This architecture i...
Daniel A. Villela, Prashant Pradhan, Dan Rubenstei...
DAC
2010
ACM
13 years 11 months ago
Eyecharts: constructive benchmarking of gate sizing heuristics
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla...