39 search results - page 6 / 8 » An Effective Bump Mapping Hardware Architecture Using Polar ... |
ASAP
2006
IEEE
14 years 1 months ago
2006
IEEE
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Linked data structure (LDS) accesses are critical to the performance of many large scale applications. Techniques have been proposed to prefetch such accesses. Unfortunately, many...
ICCSA
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. In this work, we develop novel file system, FRASH, for byteaddressable NVRAM (FRAM[1]) and NAND Flash device. Byte addressable NVRAM and NAND Flash is typified by the DRA...
ISVLSI
2005
IEEE
14 years 28 days ago
2005
IEEE
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...