72 search results - page 7 / 15 » An Efficient, Scalable Hardware Engine for Boolean SATisfiab... |
CAV
2000
Springer
14 years 1 days ago
2000
Springer
In this paper we show how to do symbolic model checking using Boolean Expression Diagrams (BEDs), a non-canonical representation for Boolean formulas, instead of Binary Decision Di...
JSA
2007
13 years 8 months ago
2007
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
ICDE
2002
IEEE
14 years 1 months ago
2002
IEEE
Soon, much of the data exchanged over the Internet will be encoded in XML, allowing for sophisticated filtering and content-based routing. We have built a filtering engine called ...
VLSISP
2010
13 years 3 months ago
2010
We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for bio...
ISQED
2002
IEEE
14 years 1 months ago
2002
IEEE
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...