ISQED 2002 - PDF Preprint Papers

ISQED 2002 International Symposium on Quality Electronic Design

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ISQED-2002 Paper

click to vote

ISQED
2002
IEEE

203views Hardware» more ISQED 2002»

Automatic Test Program Generation from RT-Level Microprocessor Descriptions

14 years 5 months ago

Download www.cad.polito.it

The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two p...

Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	203	Automatic Test Program Generation from RT-Level Microprocessor Descriptions	claim
2	175	On the Relation between SAT and BDDs for Equivalence Checking
3	168	ALBORZ: Address Level Bus Power Optimization	claim
4	137	A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits	claim
5	129	Design Method and Automation of Comparator Generation for Flash A/D Converter	claim
6	128	Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits	claim
7	126	Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning	claim
8	123	Reliable Laser Programmable Gate Array Technology	claim
9	111	Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs)	claim
10	111	Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm	claim
11	106	Trading off Reliability and Power-Consumption in Ultra-low Power Systems	claim
12	105	Measurement of Inherent Noise in EDA Tools	claim
13	105	Impact Analysis of Process Variability on Clock Skew	claim
14	103	Synthesis of Selectively Clocked Skewed Logic Circuits	claim
15	85	Optimal Sequencing Energy Allocation for CMOS Integrated Systems	claim
16	83	A Hybrid BIST Architecture and Its Optimization for SoC Testing	claim
17	74	Wireless Systems-on-a-Chip Design	claim
18	73	Promising Directions in Hardware Design Verification (invited)	claim
19	72	Inductance Aware Interconnect Scaling	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers