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DATE
2009
IEEE
149views Hardware» more  DATE 2009»
14 years 5 months ago
High level H.264/AVC video encoder parallelization for multiprocessor implementation
— H.264/AVC (Advanced Video Codec) is a new video coding standard developed by a joint effort of the ITU-TVCEG and ISO/IEC MPEG. This standard provides higher coding efficiency r...
Hajer K. Zrida, Abderrazek Jemai, Ahmed C. Ammari,...
SIGMETRICS
2008
ACM
128views Hardware» more  SIGMETRICS 2008»
13 years 11 months ago
Loss-aware network coding for unicast wireless sessions: design, implementation, and performance evaluation
Local network coding is growing in prominence as a technique to facilitate greater capacity utilization in multi-hop wireless networks. A specific objective of such local network ...
Shravan K. Rayanchu, Sayandeep Sen, Jianming Wu, S...
ISCAS
2003
IEEE
148views Hardware» more  ISCAS 2003»
14 years 4 months ago
Hybrid neural network architecture for age identification of ancient Kannada scripts
Wide research has been carried out and is still taking place in the field of character recognition of handwritten English characters. Recognizing English characters is much simple...
Harish K. Kashyap, Bansilal, P. Arun Koushik
NN
2000
Springer
192views Neural Networks» more  NN 2000»
13 years 10 months ago
A new algorithm for learning in piecewise-linear neural networks
Piecewise-linear (PWL) neural networks are widely known for their amenability to digital implementation. This paper presents a new algorithm for learning in PWL networks consistin...
Emad Gad, Amir F. Atiya, Samir I. Shaheen, Ayman E...
ERSA
2009
147views Hardware» more  ERSA 2009»
13 years 8 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias