36 search results - page 5 / 8 » An Efficient VLIW DSP Architecture for Baseband Processing |
ESTIMEDIA
2007
Springer
13 years 11 months ago
2007
Springer
Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recent...
ICCD
1999
IEEE
13 years 12 months ago
1999
IEEE
The architecture of the TriMedia CPU64 is based on the TM1000 DSPCPU. The original VLIW architecture has been extended with the concepts of vector processing and superoperations. ...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
LCTRTS
2005
Springer
14 years 1 months ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
DSRT
2008
IEEE
13 years 9 months ago
2008
IEEE
In this contribution a new system for the rapid development of real-time prototypes for digital audio signal processing algorithms on Windows PCs and a Digital Signal Processor (D...