Sciweavers

76 search results - page 7 / 16
» An Estimation Methodology for Designing Instruction Cache Me...
Sort
View
ISSS
1996
IEEE
169views Hardware» more  ISSS 1996»
13 years 11 months ago
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
Alessandro Balboni, William Fornaciari, M. Vincenz...
LCPC
2005
Springer
14 years 27 days ago
Automatic Measurement of Instruction Cache Capacity
There is growing interest in autonomic computing systems that can optimize their own behavior on different platforms without manual intervention. Examples of successful self-opti...
Kamen Yotov, Sandra Jackson, Tyler Steele, Keshav ...
WSC
1997
13 years 8 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
CODES
2001
IEEE
13 years 11 months ago
A design framework to efficiently explore energy-delay tradeoffs
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
William Fornaciari, Donatella Sciuto, Cristina Sil...
CODES
2008
IEEE
14 years 1 months ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra