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MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
14 years 2 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
ANCS
2005
ACM
14 years 2 months ago
Resource mapping and scheduling for heterogeneous network processor systems
Task to resource mapping problems are encountered during (i) hardware-software co-design and (ii) performance optimization of Network Processor systems. The goal of the first pro...
Liang Yang, Tushar Gohad, Pavel Ghosh, Devesh Sinh...
SAC
2005
ACM
14 years 2 months ago
Towards the prioritization of regression test suites with data flow information
Regression test prioritization techniques re-order the execution of a test suite in an attempt to ensure that defects are revealed earlier in the test execution phase. In prior wo...
Matthew J. Rummel, Gregory M. Kapfhammer, Andrew T...
GW
2005
Springer
161views Biometrics» more  GW 2005»
14 years 2 months ago
Captured Motion Data Processing for Real Time Synthesis of Sign Language
Abstract. The work described in this abstract presents a roadmap towards the creation and specification of a virtual humanoid capable of performing expressive gestures in real tim...
Alexis Heloir, Sylvie Gibet, Franck Multon, Nicola...
ICS
2005
Tsinghua U.
14 years 2 months ago
A performance-conserving approach for reducing peak power consumption in server systems
The combination of increasing component power consumption, a desire for denser systems, and the required performance growth in the face of technology-scaling issues are posing eno...
Wesley M. Felter, Karthick Rajamani, Tom W. Keller...