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CDES
2006
158views Hardware» more  CDES 2006»
13 years 11 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
RSP
2008
IEEE
118views Control Systems» more  RSP 2008»
14 years 4 months ago
Functional DIF for Rapid Prototyping
Dataflow formalisms have provided designers of digital signal processing systems with optimizations and guarantees to arrive at quality prototypes quickly. As system complexity in...
William Plishker, Nimish Sane, Mary Kiemb, Kapil A...
ICML
1998
IEEE
14 years 11 months ago
Q2: Memory-Based Active Learning for Optimizing Noisy Continuous Functions
This paper introduces a new algorithm, Q2, foroptimizingthe expected output ofamultiinput noisy continuous function. Q2 is designed to need only a few experiments, it avoids stron...
Andrew W. Moore, Jeff G. Schneider, Justin A. Boya...
IJON
2006
127views more  IJON 2006»
13 years 10 months ago
Evolved neural networks based on cellular automata for sensory-motor controller
Constructing the controller of a mobile robot has several issues to be addressed: how to automate behavior generation procedure, how to insert available domain knowledge effective...
Kyung-Joong Kim, Sung-Bae Cho
CCR
2004
157views more  CCR 2004»
13 years 10 months ago
Designing BGP-based outbound traffic engineering techniques for stub ASes
Today, most multi-connected autonomous systems (AS) need to control the flow of their interdomain traffic for both performance and economical reasons. This is usually done by manu...
Steve Uhlig, Olivier Bonaventure