A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs

In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier design is the 53x53 multiplication of the mantissas (52 bit mantissa+1 hidden bit). This paper proposes a approach to improve this performance bottleneck by adding a redundant 54th bit initialized to `0' in the mantissas of both multiplicand and multiplier. Now, the 54x54 bit multiplication operation is decomposed and performed by nine parallel 18x18 bit multiplication modules. The 18 bit decomposition is chosen, since nearly 512 dedicated 18x18 bit multipliers are available in the latest FPGAs. Moreover, it will be also helpful in implementing the floating point multiplier as an ASIC since the multiply operation can now be performed easily with small dedicated 18x18 bit multipliers. In the proposed architecture, one redundant 18x18 multiplier is also provided to enforce the feature of self repairability (t...

• Type: Conference
• Year: 2006
• Where: CDES
• Authors: Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
• Keywords: Bit Multiplication, Bit Multipliers, CDES 2006, CDES 2007, Dedicated 18x18 Bit