Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
This paper presents parallel algorithms for priority queue operations on a p-processor EREWPRAM. The algorithms are based on a new data structure, the Min-path Heap (MH), which is...
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Abstract Advances in high performance computing, communications, and user interfaces enable developers to construct increasingly interactive high performance applications. The Falc...
We present a set of advanced program parallelization techniques that are able to signi cantly improve the performance of application programs. We present evidence for this improve...