Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism

Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory latency caused by cache hits and misses on non-blocking architectures. In contrast, balanced scheduling schedules instructions based on an estimate of the amount of instruction-level parallelism in the program. By scheduling independent instructions behind loads based on what the program can provide, rather than what the implementation stipulates in the best case (i.e., a cache hit), balanced scheduling can hide variations in memory latencies more effectively. Since its success depends on the amount of instruction-level parallelism in the code, balanced scheduling should perform even better when more parallelism is available. In this study, we combine balanced scheduling with three compiler optimizations that increase instruction-level parallelism: loop unrolling, trace scheduling and cache locality analysis. Us...

• Type: Conference
• Year: 1995
• Where: PLDI
• Authors: Jack L. Lo, Susan J. Eggers
• Keywords: Balanced Scheduling, Cache Hit, Instruction-level Parallelism, PLDI 1995, Programming Languages