260 search results - page 32 / 52 » An FPGA Implemented Processor Architecture with Adaptive Res... |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
CCECE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents a hardware/software co-design for Multi Protocol Label Switching (MPLS) using RSVP-TE as a signaling protocol. MPLS is the protocol framework on which the atte...
CORR
2010
Springer
13 years 8 months ago
2010
Springer
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. In this paper, a novel architecture dedicated to image processing is presented. The most original aspect of the approach is the use of a System On Chip implemented in a F...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
Wireless communications requires a new approach to implement the algorithms for new standards. The computational demands of these standards are outstripping the ability of traditi...