260 search results - page 45 / 52 » An FPGA Implemented Processor Architecture with Adaptive Res... |
ICS
2007
Tsinghua U.
14 years 2 months ago
2007
Tsinghua U.
Increased complexity of memory systems to ameliorate the gap between the speed of processors and memory has made it increasingly harder for compilers to optimize an arbitrary code...
ICS
2010
Tsinghua U.
13 years 10 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
TVLSI
2008
13 years 7 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
COMSWARE
2007
IEEE
14 years 2 months ago
2007
IEEE
The Elliptic Curve Digital Signature Algorithm admits a natural parallelization wherein the point multiplication step can be split in two parts and executed in parallel. Further pa...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...