Sciweavers

1079 search results - page 105 / 216
» An Implementation of an Address Generator Using Hash Memorie...
Sort
View
CASES
2008
ACM
13 years 11 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
SAS
2007
Springer
126views Formal Methods» more  SAS 2007»
14 years 3 months ago
Hierarchical Pointer Analysis for Distributed Programs
We present a new pointer analysis for use in shared memory programs running on hierarchical parallel machines. The analysis is motivated by the partitioned global address space lan...
Amir Kamil, Katherine A. Yelick
ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
14 years 3 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
ICMCS
2008
IEEE
168views Multimedia» more  ICMCS 2008»
14 years 3 months ago
A co-design platform for algorithm/architecture design exploration
The efficient implementation of multimedia algorithms, for the ever increasing complexity of the specifications and the emergence of the new generation of processing platforms c...
Christophe Lucarz, Marco Mattavelli, Julien Dubois
MICRO
2009
IEEE
148views Hardware» more  MICRO 2009»
14 years 3 months ago
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmab...
Sangyeun Cho, Hyunjin Lee