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CONCURRENCY
2006
13 years 9 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
APN
2004
Springer
14 years 2 months ago
2004
Springer
Generating the reachability set is one of the most commonly required step when analyzing the logical or stochastic behavior of a system modeled with Petri nets. Traditional “expl...
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
Allowing loads to issue out-of-order with respect to earlier unresolved store addresses is very important for extracting parallelism in large-window superscalar processors. Blindl...
PPOPP
2010
ACM
14 years 6 months ago
2010
ACM
We present a static analysis for the automatic generation of symbolic prefetches in a transactional distributed shared memory. A symbolic prefetch specifies the first object to be...