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ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
11 years 10 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
EMSOFT
2007
Springer
14 years 1 months ago
Uniformity improving page allocation for flash memory file systems
Flash memory is a storage medium that is becoming more and more popular. Though not yet fully embraced in traditional computing systems, Flash memory is prevalent in embedded syst...
Seungjae Baek, Seongjun Ahn, Jongmoo Choi, Donghee...
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
14 years 23 days ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...
EMSOFT
2008
Springer
13 years 8 months ago
On the interplay of dynamic voltage scaling and dynamic power management in real-time embedded applications
Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM) are two popular techniques commonly employed to save energy in real-time embedded systems. DVS policies aim at red...
Vinay Devadas, Hakan Aydin
SEUS
2010
IEEE
13 years 6 months ago
Reactive Clock Synchronization for Wireless Sensor Networks with Asynchronous Wakeup Scheduling
Most of the existing clock synchronization algorithms for wireless sensor networks can be viewed as proactive clock synchronization since they require nodes to periodically synchro...
Sang Hoon Lee, Yunmook Nah, Lynn Choi