54 search results - page 8 / 11 » An Instruction Throughput Model of Superscalar Processors |
HPCA
1995
IEEE
13 years 11 months ago
1995
IEEE
The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
WCET
2008
13 years 9 months ago
2008
WCET analysis models for superscalar out-of-order CPUs generally need to be pessimistic in order to account for a wide range of possible dynamic behavior. CPU hardware modificatio...
LCPC
2004
Springer
14 years 29 days ago
2004
Springer
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
HICSS
1995
IEEE
13 years 11 months ago
1995
IEEE
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...