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ARCS
2009
Springer
14 years 3 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
SENSYS
2004
ACM
14 years 2 months ago
Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing ...
Pei Zhang, Christopher M. Sadler, Stephen A. Lyon,...
CORR
2010
Springer
224views Education» more  CORR 2010»
13 years 9 months ago
A Cluster Based Replication Architecture for Load Balancing in Peer-to-Peer Content Distribution
In P2P systems, large volumes of data are declustered naturally across a large number of peers. But it is very difficult to control the initial data distribution because every use...
S. Ayyasamy, S. N. Sivanandam
FPL
2006
Springer
103views Hardware» more  FPL 2006»
14 years 14 days ago
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification
This paper provides a realistic case study of using the previously introduced SIMPPL system architectural model, which fixes the physical interface and communication protocols bet...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
ICPP
2005
IEEE
14 years 2 months ago
Peak Power Control for a QoS Capable On-Chip Network
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum