Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
Integration of XML data is an increasingly important problem and many methods have recently been developed. In this talk, we examine the related and more challenging task of how t...
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. ...
Designing architectural frameworks without the aid of formal modeling is error prone. But, unless supported by analysis, formal modeling is prone to its own class of errors, in wh...
: We study type checking that is complete in the sense that it accepts every program whose subexpressions can all be executed without raising a type error at runtime. In a complete...