203 search results - page 14 / 41 » An O(nlogn) time algorithm for optimal buffer insertion |
TCAD
2008
13 years 7 months ago
2008
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
ICRA
2007
IEEE
14 years 1 months ago
2007
IEEE
— Modeling and scheduling of cluster tools are critical to improving the productivity and to enhancing the design of wafer processing flows and equipment for semiconductor manuf...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
SPAA
2004
ACM
14 years 24 days ago
2004
ACM
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...