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» An OR Parallel Prolog Model for Distributed Memory Systems
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LCPC
2007
Springer
14 years 3 months ago
Capsules: Expressing Composable Computations in a Parallel Programming Model
Hasnain A. Mandviwala, Umakishore Ramachandran, Ka...
IPPS
2010
IEEE
13 years 6 months ago
Fine-grained QoS scheduling for PCM-based main memory systems
With wide adoption of chip multiprocessors (CMPs) in modern computers, there is an increasing demand for large capacity main memory systems. The emerging PCM (Phase Change Memory) ...
Ping Zhou, Yu Du, Youtao Zhang, Jun Yang 0002
HPDC
2006
IEEE
14 years 3 months ago
XtremLab: A System for Characterizing Internet Desktop Grids
Desktop grid (DG) systems use the idle computing power of many volunteered desktop PC’s on the Internet to support large-scale computation and storage. For over a decade, DG sys...
Paul Malecot, Derrick Kondo, Gilles Fedak
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
14 years 15 days ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
HPCC
2009
Springer
14 years 1 months ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig