158 search results - page 17 / 32 » An Optimized Message Passing Framework for Parallel Implemen... |
PDP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
GLVLSI
2003
IEEE
14 years 28 days ago
2003
IEEE
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
FORTE
2008
13 years 9 months ago
2008
The paper studies a distributed implementation method for the BIP (Behavior, Interaction, Priority) component framework for modeling heterogeneous systems. BIP offers two powerful ...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
ICPP
1998
IEEE
13 years 12 months ago
1998
IEEE
Networks of Workstations (NOW) have become an attractive alternative platform for high performance computing. Due to the commodity nature of workstations and interconnects and due...