40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications

An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell component, a sense amplifier, and two circular shift registers for implementing refresh and read-write pointers. The sense amplifier uses bit-line decoupling to improve readout performance. Our particular application requires the storage of 800 samples of a received ultrasound signal that pass through 48 channels consisting of a preamplifier, a sample-and-hold, and an 8-bit ADC. Data is written into memory in parallel in a sequential, burst-mode fashion and read sequentially at leisure, with interspersed refresh of the memory cells. Layout and design issues concerning implementing memory in a standard 0.25 um process are discussed and simulation results are presented. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles – memory technologies. General Terms: Design.

• Type: Conference
• Year: 2003
• Where: GLVLSI
• Authors: Michael I. Fuller, James P. Mabry, John A. Hossack, Travis N. Blalock
• Keywords: GLVLSI 2003, Memory Cell Component, Memory Cells, Sense Amplifier, VLSI