37 search results - page 5 / 8 » An analytical model for software-only main memory compressio... |
ICDE
2005
IEEE
14 years 8 months ago
2005
IEEE
Hardware cache behavior is an important factor in the performance of memory-resident, data-intensive systems such as XML filtering engines. A key data structure in several recent ...
CODES
2008
IEEE
14 years 1 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
EUROPAR
1999
Springer
13 years 11 months ago
1999
Springer
For complex queries in parallel database systems, substantial amounts of data must be redistributed between operators executed on different processing nodes. Frequently, such inter...
JUCS
2000
13 years 7 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...