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» An efficient terminal and model order reduction algorithm
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ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
14 years 5 months ago
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheld...
KDD
2006
ACM
113views Data Mining» more  KDD 2006»
14 years 9 months ago
A new efficient probabilistic model for mining labeled ordered trees
Mining frequent patterns is a general and important issue in data mining. Complex and unstructured (or semi-structured) datasets have appeared in major data mining applications, i...
Kosuke Hashimoto, Kiyoko F. Aoki-Kinoshita, Nobuhi...
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 7 months ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
SCL
2008
105views more  SCL 2008»
13 years 9 months ago
Computation of nonlinear balanced realization and model reduction based on Taylor series expansion
In this paper a computational algorithm for nonlinear balanced realization and model reduction based on Taylor series expansion is proposed. This algorithm requires recursive comp...
Kenji Fujimoto, Daisuke Tsubakino
ET
2010
113views more  ET 2010»
13 years 6 months ago
Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study
Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often ...
Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Che...