ASPDAC 2010 - PDF Preprint Papers

ASPDAC 2010 Asia and South Pacific Design Automation Conference

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ASPDAC
2010
ACM

637views Hardware» more ASPDAC 2010»

A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography

13 years 10 months ago

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As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this pape...

Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, D...

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Id	Views	Title	Status

1	637	A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography	claim
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7	183	Multi-operand adder synthesis on FPGAs using generalized parallel counters	claim
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9	170	An adaptive parallel flow for power distribution network simulation using discrete Fourier transform	claim
10	170	A 60GHz direct-conversion transmitter in 65nm CMOS technology	claim
11	169	Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits	claim
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13	168	Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs	claim
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22	152	Slack redistribution for graceful degradation under voltage overscaling	claim
23	151	Source-level timing annotation for fast and accurate TLM computation model generation	claim
24	150	Post-silicon debugging for multi-core designs	claim
25	147	Rule-based optimization of reversible circuits	claim
26	144	Correlating system test Fmax with structural test Fmax and process monitoring measurements	claim
27	143	Constrained global scheduling of streaming applications on MPSoCs	claim
28	143	Optimizing power and performance for reliable on-chip networks	claim
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30	142	Application-specific 3D Network-on-Chip design using simulated allocation	claim
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48	129	System-level development of embedded software	claim
49	128	Adaptive power management for real-time event streams	claim
50	127	Data learning based diagnosis	claim
51	126	Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization	claim
52	125	Graph partition based path selection for testing of small delay defects	claim
53	125	Design and chip implementation of an instruction scheduling free ubiquitous processor	claim
54	124	MuCCRA-3: a low power dynamically reconfigurable processor array	claim
55	123	Dynamic and adaptive allocation of applications on MPSoC platforms	claim
56	123	Trace-based performance analysis framework for heterogeneous multicore systems	claim
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59	121	Current source modeling in the presence of body bias	claim
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62	119	VISA: versatile impulse structure approximation for time-domain linear macromodeling	claim
63	119	iRetILP: an efficient incremental algorithm for min-period retiming under general delay model	claim
64	119	Functional and partially-functional skewed-load tests	claim
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67	115	A versatile recognition processor for sensor network applications	claim
68	112	Optimizing blocks in an SoC using symbolic code-statement reachability analysis	claim
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70	110	An alternative polychronous model and synthesis methodology for model-driven embedded software	claim
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80	94	Technology mapping with crosstalk noise avoidance	claim

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