This paper presents a bounded model checking algorithm for the verification of analog and mixed-signal (AMS) circuits using a satisfiability modulo theories (SMT) solver. The sys...
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
We demonstrate an algorithmfor interconnect modeling in rhe presence ofprocess variation based on extension of the truncated balanced realizationmodel reduction algorithmto multi-...
RLC circuits have been shown to be better formulated as second-order systems instead of first-order systems. The corresponding model order reduction techniques for secondorder sys...
Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGau...
The interaction among concurrently executing threads of a program results in insidious programming errors that are difficult to reproduce and fix. Unfortunately, the problem of ve...