310 search results - page 15 / 62 » An error bound for model reduction of Lur'e-type systems |
ATVA
2007
Springer
14 years 2 months ago
2007
Springer
This paper presents a bounded model checking algorithm for the verification of analog and mixed-signal (AMS) circuits using a satisfiability modulo theories (SMT) solver. The sys...
GLVLSI
2007
IEEE
14 years 9 days ago
2007
IEEE
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
We demonstrate an algorithmfor interconnect modeling in rhe presence ofprocess variation based on extension of the truncated balanced realizationmodel reduction algorithmto multi-...
DAC
2007
ACM
14 years 11 days ago
2007
ACM
RLC circuits have been shown to be better formulated as second-order systems instead of first-order systems. The corresponding model order reduction techniques for secondorder sys...
TACAS
2005
Springer
14 years 1 months ago
2005
Springer
The interaction among concurrently executing threads of a program results in insidious programming errors that are difficult to reproduce and fix. Unfortunately, the problem of ve...