ICCAD 2004 - PDF Preprint Papers

ICCAD 2004 International Conference on Computer-Aided Design

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ICCAD
2004
IEEE

260views Hardware» more ICCAD 2004»

On interactions between routing and detailed placement

14 years 8 months ago

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The main goal of this paper is to develop deeper insights into viable placement-level optimization of routing. Two primary contributions are made. First, an experimental framework...

Devang Jariwala, John Lillis

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Id	Views	Title	Status

1	260	On interactions between routing and detailed placement	claim
2	191	Checking consistency of C and Verilog using predicate abstraction and induction	claim
3	180	Physical placement driven by sequential timing analysis	claim
4	158	DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs	claim
5	155	Robust analog/RF circuit design with projection-based posynomial modeling	claim
6	155	A flexibility aware budgeting for hierarchical flow timing closure	claim
7	151	Dynamic range estimation for nonlinear systems	claim
8	150	Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth	claim
9	150	Cost-effective radiation hardening technique for combinational logic	claim
10	147	Interval-valued reduced order statistical interconnect modeling	claim
11	145	Accurate estimation of global buffer delay within a floorplan	claim
12	145	Asymptotic probability extraction for non-normal distributions of circuit performance	claim
13	142	Variational interconnect analysis via PMTBR	claim
14	141	The effects of energy management on reliability in real-time embedded systems	claim
15	139	Fast simulation of VLSI interconnects	claim
16	138	A thermal-driven floorplanning algorithm for 3D ICs	claim
17	135	Soft self-synchronising codes for self-calibrating communication	claim
18	134	An analytic placer for mixed-size placement and timing-driven placement	claim
19	134	Engineering details of a stable force-directed placer	claim
20	130	Routability-driven placement and white space allocation	claim
21	128	Power estimation for cycle-accurate functional descriptions of hardware	claim
22	127	A yield improvement methodology using pre- and post-silicon statistical clock scheduling	claim
23	126	Configuration bitstream compression for dynamically reconfigurable FPGAs	claim
24	125	Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems	claim
25	125	Temporal floorplanning using the T-tree formulation	claim
26	124	FLUTE: fast lookup table based wirelength estimation technique	claim
27	124	Architectural-level synthesis of digital microfluidics-based biochips	claim
28	123	Logical effort based technology mapping	claim
29	121	Factoring and eliminating common subexpressions in polynomial expressions	claim
30	120	A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance	claim
31	118	Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization	claim
32	115	Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation	claim
33	114	Simultaneous short-path and long-path timing optimization for FPGAs	claim
34	114	High-level synthesis using computation-unit integrated memories	claim
35	113	High-level synthesis: an essential ingredient for designing complex ASICs	claim
36	113	Vdd programmability to reduce FPGA interconnect power	claim
37	113	Static statistical timing analysis for latch-based pipeline designs	claim
38	111	A new incremental placement algorithm and its application to congestion-aware divisor extraction	claim
39	110	Wire-length prediction using statistical techniques	claim
40	109	Hardware/software managed scratchpad memory for embedded system	claim
41	107	Computation of signal threshold crossing times directly from higher order moments	claim
42	106	Design space exploration for a UMTS front-end exploiting analog platforms	claim
43	102	True crosstalk aware incremental placement with noise map	claim
44	101	Frugal linear network-based test decompression for drastic test cost reductions	claim
45	100	DynamoSim: a trace-based dynamically compiled instruction set simulator	claim
46	100	A chip-level electrostatic discharge simulation strategy	claim
47	99	SPIN-TEST: automatic test pattern generation for speed-independent circuits	claim
48	97	Statistical design and optimization of SRAM cell for yield enhancement	claim
49	96	M-trie: an efficient approach to on-chip logic minimization	claim
50	95	Low-power programmable routing circuitry for FPGAs	claim
51	95	Energy optimization for a two-device data flow chain	claim
52	94	Timing macro-modeling of IP blocks with crosstalk	claim
53	91	SILENT: serialized low energy transmission coding for on-chip interconnection networks	claim
54	88	Unification of partitioning, placement and floorplanning	claim
55	88	Diagnosis of small-signal parameters for broadband amplifiers through S-parameter measurements and sensitivity-guided evolutionary search	claim
56	88	Interconnect lifetime prediction under dynamic stress for reliability-aware design	claim
57	87	A quantitative study and estimation models for extensible instructions in embedded processors	claim
58	87	A vectorless estimation of maximum instantaneous current for sequential circuits	claim
59	87	Exploiting level sensitive latches in wire pipelining	claim
60	85	Improving soft-error tolerance of FPGA configuration bits	claim
61	83	Custom-optimized multiplierless implementations of DSP algorithms	claim
62	80	HiSIM: hierarchical interconnect-centric circuit simulator	claim
63	80	Techniques for improving the accuracy of geometric-programming based analog circuit design optimization	claim
64	64	Simultaneous design and placement of multiplexed chemical processing systems on microchips	claim
65	61	Timing analysis considering spatial power/ground level variation	claim

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