Sciweavers

139 search results - page 17 / 28
» An evolutionary algorithm for reducing integrated-circuit te...
Sort
View
ITC
2002
IEEE
114views Hardware» more  ITC 2002»
14 years 14 days ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
ICISC
2004
169views Cryptology» more  ICISC 2004»
13 years 9 months ago
ADWICE - Anomaly Detection with Real-Time Incremental Clustering
Abstract. Anomaly detection, detection of deviations from what is considered normal, is an important complement to misuse detection based on attack signatures. Anomaly detection in...
Kalle Burbeck, Simin Nadjm-Tehrani
ERSA
2006
197views Hardware» more  ERSA 2006»
13 years 9 months ago
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
High frame rate video capture and image processing is an important capability for applications in defense and homeland security where incoming missiles must be detected in very sh...
Vinay Sriram, David Kearney
DAC
2005
ACM
14 years 8 months ago
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...
Sorin Manolache, Petru Eles, Zebo Peng
GPEM
2008
98views more  GPEM 2008»
13 years 7 months ago
Sporadic model building for efficiency enhancement of the hierarchical BOA
Efficiency enhancement techniques--such as parallelization and hybridization--are among the most important ingredients of practical applications of genetic and evolutionary algori...
Martin Pelikan, Kumara Sastry, David E. Goldberg