ITC 2002 - PDF Preprint Papers

ITC 2002 International Test Conference

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ITC-2002 Paper

click to vote

ITC
2002
IEEE

143views Hardware» more ITC 2002»

BIST-Based Diagnosis of FPGA Interconnect

14 years 4 months ago

Download www.eng.auburn.edu

: We present a Built-In Self-Test (BIST)-based diagnostic approach for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) that can be used for either...

Charles E. Stroud, Jeremy Nall, Matthew Lashinsky,...

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	143	BIST-Based Diagnosis of FPGA Interconnect	claim
2	135	Test Coverage: What Does It Mean When a Board Test Passes?	claim
3	133	A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits	claim
4	127	A New Test Generation Approach for Embedded Analogue Cores in SoC	claim
5	114	Scan Power Reduction Through Test Data Transition Frequency Analysis	claim
6	112	Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis	claim
7	102	Adapting an SoC to ATE Concurrent Test Capabilities	claim
8	102	Fault Grading FPGA Interconnect Test Configurations	claim
9	99	Verifying Properties Using Sequential ATPG	claim
10	99	An Embedded Core for Sub-Picosecond Timing Measurements	claim
11	98	An Effective Diagnosis Method to Support Yield Improvement	claim
12	98	A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets	claim
13	97	A Multi-Language Goal-Tree Based Functional Test Planning System	claim
14	97	RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST	claim
15	94	Techniques to Reduce Data Volume and Application Time for Transition Test	claim
16	88	Embedded Deterministic Test for Low-Cost Manufacturing Test	claim
17	86	Incremental Diagnosis of Multiple Open-Interconnects	claim
18	84	Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems	claim
19	83	Packet-Based Input Test Data Compression Techniques	claim
20	81	Design Rewiring Using ATPG	claim
21	80	Screening MinVDD Outliers Using Feed-Forward Voltage Testing	claim
22	77	Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor	claim
23	72	Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers