139 search results - page 19 / 28 » An evolutionary algorithm for reducing integrated-circuit te... |
102
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ISCAS
2003
IEEE
15 years 8 months ago
2003
IEEE
In this paper, we study the effectiveness of the multilevel paradigm in considerably reducing the diagnosis latency of distributed algorithms for fault detection in networks with ...
142
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ICCS
2001
Springer
15 years 8 months ago
2001
Springer
Abstract. Phylogeny reconstruction from molecular data poses complex optimization problems: almost all optimization models are NP-hard and thus computationally intractable. Yet app...
160
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CONIELECOMP
2011
IEEE
14 years 7 months ago
2011
IEEE
This work focuses on developing systems of blocks in SIMULINK and VHDL to reuse on design of applications involving the recognition of polygonal objects. Usage of this work reduce...
143
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BMCBI
2005
15 years 3 months ago
2005
Background: Pairwise stochastic context-free grammars (Pair SCFGs) are powerful tools for evolutionary analysis of RNA, including simultaneous RNA sequence alignment and secondary...
137
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ISCA
1994
IEEE
15 years 7 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...