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TVLSI
2008
164views more  TVLSI 2008»
13 years 7 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
HPCA
2009
IEEE
14 years 8 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
PPOPP
2003
ACM
14 years 22 days ago
Impala: a middleware system for managing autonomic, parallel sensor systems
Sensor networks are long-running computer systems with many sensing/compute nodes working to gather information about their environment, process and fuse that information, and in ...
Ting Liu, Margaret Martonosi
VTC
2010
IEEE
201views Communications» more  VTC 2010»
13 years 5 months ago
iTETRIS: Adaptation of ITS Technologies for Large Scale Integrated Simulation
1 —the European Union (EU) Framework Program 7 (FP7) funded project, iTETRIS [1] (An Integrated Wireless and Traffic Platform for Real-Time Road Traffic Management Solutions) tar...
Vineet Kumar, Lan Lin, Daniel Krajzewicz, Fatma Hr...
EDO
2005
Springer
14 years 1 months ago
Generating connectors for heterogeneous deployment
re connector is an abstraction capturing interactions among components. Apart from middleware independence, connectors provide additional services (e.g., adaptation, synchronizati...
Ondrej Galik, Tomás Bures