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» An improvement in formal verification
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ICCS
2007
Springer
14 years 4 months ago
Equivalent Semantic Translation from Parallel DEVS Models to Time Automata
Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS ...
Shoupeng Han, Kedi Huang
TCAD
2008
181views more  TCAD 2008»
13 years 9 months ago
A Survey of Automated Techniques for Formal Software Verification
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
Vijay D'Silva, Daniel Kroening, Georg Weissenbache...
JOT
2007
169views more  JOT 2007»
13 years 9 months ago
Translating AUML Diagrams into Maude Specifications: A Formal Verification of Agents Interaction Protocols
Agents Interaction Protocols (AIPs) play a crucial role in multi-agents systems development. They allow specifying sequences of messages between agents. Major proposed protocols s...
Farid Mokhati, Noura Boudiaf, Mourad Badri, Linda ...
IFIP13
2004
13 years 11 months ago
Formal Verification and Validation of Interactive Systems Specifications
: This paper proposes a development process for interactive systems based both on verification and validation methods. Our approach is formal and use at first the B Method. We show...
Yamine Aït Ameur, Benoit Breholée, Pat...
EURODAC
1994
IEEE
113views VHDL» more  EURODAC 1994»
14 years 2 months ago
Formal verification of pipeline conflicts in RISC processors
We outline a general methodology for the formal verification of pipeline conflicts in RISC cores. The different kinds of conflicts that can occur due to the simultaneous execution...
Ramayya Kumar, Sofiène Tahar