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ISCA
1996
IEEE
102views Hardware» more  ISCA 1996»
13 years 11 months ago
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, He...
TCOS
2010
13 years 2 months ago
Green Secure Processors: Towards Power-Efficient Secure Processor Design
With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the softwar...
Siddhartha Chhabra, Yan Solihin
FMSD
2002
107views more  FMSD 2002»
13 years 7 months ago
Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function
We present a new technique for verification of complex hardware devices that allows both generality andahighdegreeofautomation.Thetechniqueisbasedonournewwayofconstructinga"li...
Sergey Berezin, Edmund M. Clarke, Armin Biere, Yun...
MICRO
2002
IEEE
124views Hardware» more  MICRO 2002»
14 years 10 days ago
Optimizing pipelines for power and performance
During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performan...
Viji Srinivasan, David Brooks, Michael Gschwind, P...
VLSI
2012
Springer
12 years 3 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel