MICRO 2002 - PDF Preprint Papers

MICRO 2002 IEEE/ACM International Symposium on Microarchitecture

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MICRO
2002
IEEE

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Standardization and Competitive Advantage

14 years 4 days ago

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Richard H. Stern

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Id	Views	Title	Status

1	195	Standardization and Competitive Advantage	claim
2	173	Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks	claim
3	171	Orion: a power-performance simulator for interconnection networks	claim
4	164	A quantitative framework for automated pre-execution thread selection	claim
5	161	The Basics of Performance-Monitoring Hardware	claim
6	159	Master/slave speculative parallelization	claim
7	157	The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs	claim
8	156	TCP Switching: Exposing Circuits to IP	claim
9	143	Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor	claim
10	131	Pointer cache assisted prefetching	claim
11	131	Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware	claim
12	131	Mica: A Wireless Platform for Deeply Embedded Networks	claim
13	130	Ubiquitous Spatial-Information Services Using Cell Phones	claim
14	128	Compiler-directed instruction cache leakage optimization	claim
15	127	DELI: a new run-time control point	claim
16	124	Optimizing pipelines for power and performance	claim
17	124	CAN for Critical Embedded Automotive Networks	claim
18	123	The Ride Before the Fall	claim
19	123	Efficient Randomized Algorithms for Input-Queued Switch Scheduling	claim
20	122	Microarchitectural denial of service: insuring microarchitectural fairness	claim
21	121	Convergent scheduling	claim
22	119	Reduced code size modulo scheduling in the absence of hardware support	claim
23	119	Microarchitectural support for precomputation microthreads	claim
24	118	Exploiting data-width locality to increase superscalar execution bandwidth	claim
25	117	Generating physical addresses directly for saving instruction TLB energy	claim
26	117	Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction	claim
27	115	The Test of Time	claim
28	114	Characterizing and predicting value degree of use	claim
29	114	An Implementable Parallel Scheduler for Input-Queued Switches	claim
30	113	Vacuum packing: extracting hardware-detected program phases for post-link optimization	claim
31	113	Enterprise Computing	claim
32	111	Managing static leakage energy in microprocessor functional units	claim
33	111	Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture	claim
34	109	Using modern graphics architectures for general-purpose computing: a framework and analysis	claim
35	108	Dynamic frequency and voltage control for a multiple clock domain microarchitecture	claim
36	108	Is Gatoring Unfair or Illegal?	claim
37	105	Power protocol: reducing power dissipation on off-chip data buses	claim
38	104	Compiling for instruction cache performance on a multithreaded architecture	claim
39	104	Reducing register ports for higher speed and lower energy	claim
40	103	Cherry: checkpointed early resource recycling in out-of-order microprocessors	claim
41	103	The Quadrics Network: High-Performance Clustering Technology	claim
42	100	Microarchitectural exploration with Liberty	claim
43	97	Instruction fetch deferral using static slack	claim
44	97	Three extensions to register integration	claim
45	97	Challenging search engines under copyright law: Part 1	claim
46	94	FTC Piles onto Rambus' Standardization Skullduggery	claim

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