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FPL
2009
Springer
106views Hardware» more  FPL 2009»
13 years 11 months ago
An ASIC perspective on FPGA optimizations
In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect t...
Andreas Ehliar, Dake Liu
ASPLOS
2008
ACM
13 years 9 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August
DAC
2011
ACM
12 years 7 months ago
Customer-aware task allocation and scheduling for multi-mode MPSoCs
Today’s multiprocessor system-on-a-chip (MPSoC) products typically have multiple execution modes, and for each mode, all the products utilize the same task allocation and schedu...
Lin Huang, Rong Ye, Qiang Xu
CSCLP
2004
Springer
14 years 1 months ago
Characterization of a New Restart Strategy for Randomized Backtrack Search
We propose an improved restart strategy for randomized backtrack search, and evaluate its performance by comparing to other heuristic and stochastic search techniques for solving r...
Venkata Praveen Guddeti, Berthe Y. Choueiry
IPPS
2002
IEEE
14 years 18 days ago
Hierarchical Interconnects for On-Chip Clustering
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
Aneesh Aggarwal, Manoj Franklin