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HPCA
2006
IEEE
14 years 9 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
IEEEPACT
2006
IEEE
14 years 3 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
ICPPW
2007
IEEE
14 years 3 months ago
Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
Gang Qu
IMC
2004
ACM
14 years 2 months ago
Bandwidth estimation in broadband access networks
There has been much work on developing techniques for estimating the capacity and the available bandwidth of network paths based on end-point measurements. The focus has primarily...
Karthik Lakshminarayanan, Venkata N. Padmanabhan, ...
APCSAC
2001
IEEE
14 years 19 days ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li