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» An on Chip ADC Test Structure
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VTS
2006
IEEE
116views Hardware» more  VTS 2006»
14 years 1 months ago
Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding
A technique is presented here for improving the compression achieved with any linear decompressor by adding a small non-linear decoder that exploits bit-wise and pattern-wise corr...
Jinkyu Lee, Nur A. Touba
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
14 years 11 days ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey
ADC
2003
Springer
182views Database» more  ADC 2003»
14 years 21 days ago
CT-ITL : Efficient Frequent Item Set Mining Using a Compressed Prefix Tree with Pattern Growth
Discovering association rules that identify relationships among sets of items is an important problem in data mining. Finding frequent item sets is computationally the most expens...
Yudho Giri Sucahyo, Raj P. Gopalan
ASPDAC
2006
ACM
88views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation
— A substrate-coupling equivalent circuit can be derived for an arbitrary guard ring test structure by way of F-matrix computation. The derived netlist represents a unified impe...
Daisuke Kosaka, Makoto Nagata
GLOBECOM
2009
IEEE
13 years 11 months ago
Efficient Multicast Support in Buffered Crossbars using Networks on Chip
The Internet growth coupled with the variety of its services is creating an increasing need for multicast traffic support by backbone routers and packet switches. Recently, buffere...
Iria Varela Senin, Lotfi Mhamdi, Kees Goossens