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WMPI
2004
ACM
14 years 29 days ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
IPPS
2006
IEEE
14 years 1 months ago
Parallelization of module network structure learning and performance tuning on SMP
As an extension of Bayesian network, module network is an appropriate model for inferring causal network of a mass of variables from insufficient evidences. However learning such ...
Hongshan Jiang, Chunrong Lai, Wenguang Chen, Yuron...
ICRA
2010
IEEE
185views Robotics» more  ICRA 2010»
13 years 6 months ago
MOPED: A scalable and low latency object recognition and pose estimation system
— The latency of a perception system is crucial for a robot performing interactive tasks in dynamic human environments. We present MOPED, a fast and scalable perception system fo...
Manuel Martinez, Alvaro Collet, Siddhartha S. Srin...
CCGRID
2007
IEEE
14 years 1 months ago
Design of a Scalable Peer-to-Peer Information System Using the GT4 Index Service
Grid applications need efficient access to information about available resources and services. Typically, this access is provided by information services that are often organized ...
Shishir Bharathi, Ann L. Chervenak
PPOPP
2009
ACM
14 years 8 months ago
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors
Recent advances in polyhedral compilation technology have made it feasible to automatically transform affine sequential loop nests for tiled parallel execution on multi-core proce...
Muthu Manikandan Baskaran, Nagavijayalakshmi Vydya...