118 search results - page 5 / 24 » Analysis and Minimization of Test Time in a Combined BIST an... |
MTV
2007
IEEE
14 years 1 months ago
2007
IEEE
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
ETS
2007
IEEE
14 years 1 months ago
2007
IEEE
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare r...
IOLTS
2002
IEEE
13 years 11 months ago
2002
IEEE
This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuit...
KDD
2000
ACM
13 years 10 months ago
2000
ACM
We describe an application of data mining and decision analysis to the problem of die-level functional test in integrated circuit manufacturing. Integrated circuits are fabricated...
ICDM
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper describes an approach for incorporating externally specified aggregate ratings information into certain types of collaborative filtering (CF) methods. For a statistic...