Reduction of Power Dissipation during Scan Testing by Test Vector Ordering

Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transitions requires exhaustive simulation of each test vector pair. However, long simulation time makes this approach impractical for circuits with large test set. In this paper we present a calculation based approach to faster order test vectors to reduce test power for full scan sequential circuits. Most calculation approaches are for combinational circuits or for sequential circuits but only considering the portion of circuit derived from the primary inputs. The proposed approach exploits the dependencies between internal circuits and transitions at both the primary and state inputs. Experiments performed on the ISCAS 89 benchmark circuits show that the improvement efficiency of

• Type: Conference
• Year: 2007
• Where: MTV
• Authors: Wang-Dauh Tseng, Lung-Jen Lee
• Keywords: Hardware, MTV 2007, Sequential Circuits, Test Vector Ordering, Test Vectors