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ISCA
2008
IEEE
150views Hardware» more  ISCA 2008»
14 years 1 months ago
Fetch-Criticality Reduction through Control Independence
Architectures that exploit control independence (CI) promise to remove in-order fetch bottlenecks, like branch mispredicts, instruction-cache misses and fetch unit stalls, from th...
Mayank Agarwal, Nitin Navale, Kshitiz Malik, Matth...
IPPS
1999
IEEE
13 years 11 months ago
Experimental Evaluation of QSM, a Simple Shared-Memory Model
Parallel programming models should attempt to satisfy two conflicting goals. On one hand, they should hide architectural details so that algorithm designers can write simple, port...
Brian Grayson, Michael Dahlin, Vijaya Ramachandran
DAC
2007
ACM
14 years 8 months ago
Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors
Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultralow-power designs may even permit embedded systems...
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert ...
SAMOS
2005
Springer
14 years 28 days ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 4 months ago
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
Xiaoyao Liang, Kerem Turgay, David Brooks