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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 11 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ARCS
2006
Springer
13 years 11 months ago
An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks
Abstract. Dynamic hardware reconfiguration is becoming a key technology in embedded system design that offers among others new potentials in dependable computing. To make system de...
Dirk Koch, Thilo Streichert, Steffen Dittrich, Chr...
IESS
2007
Springer
124views Hardware» more  IESS 2007»
14 years 1 months ago
Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning
: Hardware/software partitioning moves software kernels from a microprocessor to custom hardware accelerators. We consider advanced implementation options for accelerators, greatly...
Scott Sirowy, Frank Vahid
ICESS
2007
Springer
14 years 1 months ago
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator
In an embedded system including a base processor integrated with a tightly coupled accelerator, extracting frequently executed portions of the code (hot portion) and executing thei...
Hamid Noori, Farhad Mehdipour, Morteza Saheb Zaman...