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IPPS
2005
IEEE
14 years 4 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
IPPS
2008
IEEE
14 years 4 months ago
Translational research design templates, Grid computing, and HPC
Design templates that involve discovery, analysis, and integration of information resources commonly occur in many scientific research projects. In this paper we present examples o...
Joel H. Saltz, Scott Oster, Shannon Hastings, Step...
IPPS
2006
IEEE
14 years 4 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
SBACPAD
2003
IEEE
103views Hardware» more  SBACPAD 2003»
14 years 3 months ago
Performance Analysis Issues for Parallel Implementations of Propagation Algorithm
This paper presents a theoretical study to evaluate the performance of a family of parallel implementations of the propagation algorithm. The propagation algorithm is used to an i...
Leonardo Brenner, Luiz Gustavo Fernandes, Paulo Fe...
CORR
2008
Springer
73views Education» more  CORR 2008»
13 years 10 months ago
Stiffness Analysis of 3-d.o.f. Overconstrained Translational Parallel Manipulators
The paper presents a new stiffness modelling method for overconstrained parallel manipulators, which is applied to 3-d.o.f. translational mechanisms. It is based on a multidimensio...
Anatoly Pashkevich, Damien Chablat, Philippe Wenge...