657 search results - page 63 / 132 » Analysis of Multithreaded Architectures for Parallel Computi... |
HPCA
1999
IEEE
14 years 2 months ago
1999
IEEE
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
AINA
2006
IEEE
14 years 4 months ago
2006
IEEE
: A newly emerging protocol for storage networking, iSCSI [1,2], was recently ratified by the Internet Engineering Task Force [3]. The iSCSI protocol is perceived as a low cost alt...
HPCA
2007
IEEE
14 years 10 months ago
2007
IEEE
Task-selection policies are critical to the performance of any architecture that uses speculation to extract parallel tasks from a sequential thread. This paper demonstrates that ...
PPOPP
2009
ACM
14 years 11 months ago
2009
ACM
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
CC
2010
Springer
14 years 5 months ago
2010
Springer
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...