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IESS
2007
Springer
120views Hardware» more  IESS 2007»
14 years 1 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
DSN
2004
IEEE
13 years 11 months ago
Impact of Path Diversity on Multi-homed and Overlay Networks
Multi-homed and overlay networks are two widely studied approaches aimed at leveraging the inherent redundancy of the Internet's underlying routing infrastructure to enhance ...
Junghee Han, Farnam Jahanian
FCCM
2005
IEEE
102views VLSI» more  FCCM 2005»
14 years 1 months ago
A Signature Match Processor Architecture for Network Intrusion Detection
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). NIDSs are becoming critical components of the network infrastructu...
Janardhan Singaraju, Long Bu, John A. Chandy
MOBIHOC
2010
ACM
13 years 5 months ago
On quality of monitoring for multi-channel wireless infrastructure networks
Passive monitoring utilizing distributed wireless sniffers is an effective technique to monitor activities in wireless infrastructure networks for fault diagnosis, resource manage...
Arun Chhetri, Huy Anh Nguyen, Gabriel Scalosub, Ro...
TC
2010
13 years 5 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers