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» Analysis of a reconfigurable network processor
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DATE
2005
IEEE
104views Hardware» more  DATE 2005»
14 years 1 months ago
Queue Management in Network Processors
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
Ioannis Papaefstathiou, Theofanis Orphanoudakis, G...
ASAP
2005
IEEE
133views Hardware» more  ASAP 2005»
14 years 1 months ago
Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware
In this paper, we propose a hardware/software partitioning method for improving applications’ performance in embedded systems. Critical software parts are accelerated on hardwar...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...
ASAP
2004
IEEE
124views Hardware» more  ASAP 2004»
13 years 11 months ago
Biosequence Similarity Search on the Mercury System
Biosequence similarity search is an important application in modern molecular biology. Search algorithms aim to identify sets of sequences whose extensional similarity suggests a c...
Praveen Krishnamurthy, Jeremy Buhler, Roger D. Cha...
DSN
2005
IEEE
14 years 1 months ago
Assured Reconfiguration of Fail-Stop Systems
Hardware dependability improvements have led to a situation in which it is sometimes unnecessary to employ extensive hardware replication to mask hardware faults. Expanding upon o...
Elisabeth A. Strunk, John C. Knight, M. Anthony Ai...
FPL
2006
Springer
108views Hardware» more  FPL 2006»
13 years 11 months ago
Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
James Moscola, Young H. Cho, John W. Lockwood