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» Analysis of communication delay bounds for network on chips
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ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
14 years 3 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
ICC
2009
IEEE
105views Communications» more  ICC 2009»
14 years 3 months ago
Decentralized Control and Optimization of Networks with QoS-Constrained Services
—We consider data networks in which real-time/near real-time applications require not only successful transmission of packets from source to destination, but also specific end-to...
Iraj Saniee
INFOCOM
2002
IEEE
14 years 1 months ago
Application of Network Calculus to General Topologies using Turn-Prohibition
Abstract— Network calculus is known to apply in general only to feedforward routing networks, i.e., networks where routes do not create cycles of interdependent packet flows. In...
David Starobinski, Mark G. Karpovsky, Lev Zakrevsk...
GLOBECOM
2008
IEEE
14 years 3 months ago
An Upper Bound on Network Size in Mobile Ad-Hoc Networks
—In this paper we propose a model to compute an upper bound for the maximum network size in mobile ad-hoc networks. Our model is based on the foundation that for a unicast route ...
Michael Pascoe, Javier Gomez, Victor Rangel, Migue...
CCECE
2006
IEEE
14 years 3 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya