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» Analysis of communication delay bounds for network on chips
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VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
14 years 9 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
EUROPAR
2005
Springer
14 years 2 months ago
New Bounds on the Competitiveness of Randomized Online Call Control in Cellular Networks
Abstract. We address the call control problem in wireless cellular networks that utilize Frequency Division Multiplexing (FDM) technology. In such networks, many users within the s...
Ioannis Caragiannis, Christos Kaklamanis, Evi Papa...
ISCC
2005
IEEE
130views Communications» more  ISCC 2005»
14 years 2 months ago
Fair and Efficient Frame-Based Scheduling Algorithm for Multimedia Networks
The broad spread of packet data networks and the emergence of applications in multimedia communications, created a driving force towards an improved Quality of Service (QoS) model...
T. Al-Khasib, Hussein M. Alnuweiri, Hossam Fattah,...
IPPS
2003
IEEE
14 years 2 months ago
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
Daniel Wiklund, Dake Liu
MSWIM
2009
ACM
14 years 3 months ago
HUBCODE: message forwarding using hub-based network coding in delay tolerant networks
Most people-centric delay tolerant networks have been shown to exhibit power-law behavior. Analysis of the temporal connectivity graph of such networks reveals the existence of hu...
Shabbir Ahmed, Salil S. Kanhere